ge ne ra l de sc ript ion the max3953 is a 9.953gbps/10.3125gbps 1:16 dese- rializer with clock recovery for 10gbps ethernet an d oc192 sonet applications. the integrated phase- locked loop (pll) recovers a clock from the serial data input, and the data is then retimed and demultiplex ed into 16 parallel lvds outputs. using maxims sige bipolar process, the max3953 can achieve 0.75ui of high-frequency jitter tolerance comprised of 0.50ui of deterministic jitter and 0.25ui of random jitter. the max3953 includes ttl-compatible loss-of-lock ( lol ) and sync-error (sync_err) indicators that allow the user to verify that the part has locked on to i ncoming data. in case the incoming data becomes invalid, a clock holdover function is provided to maintain a v alid reference clock to the upstream device. for proper operation, a reference clock of baud rate/64 or bau d rate/16 is required. the max3953 operates from a single +3.3v power sup- ply and typically dissipates 1.5w. the operating te m- perature range is from 0c to +85c. the max3953 is available in a 68-pin qfn package. applic a t ions 10gbps ethernet lan 10gbps ethernet wan add/drop multiplexers digital cross-connects fe a t ure s ? serial data rate: 9.953gbps/10.3125gbps ? clock recovery with 1:16 demultiplexer ? 0.75ui p-p high-frequency jitter tolerance ? 16-bit parallel lvds output ? oif-compliant parallel interface ? loss-of-lock ( lol ) indicator ? differential input range: 100mv p-p to 1.2v p-p ? clock holdover ? reference clock: baud rate/64 or baud rate/16 ? temperature range: 0c to +85c ? 10mm ? 10mm 68-pin qfn package m ax 3 9 5 3 1 0 gbps 1 :1 6 de se ria lize r w it h cloc k re c ove ry ________________________________________________________________ maxim integrated products 1 orde ring i nform a t ion max3953 max3970 max3971a gnd clksel los_in pdoi5+ rateset fil refclk+ refclk- sdi+ sdi- v cc v cc refset +3.3v 0.047 f sync_err overhead termination lol pclk0- pclk0+ pdo0- pdo0+ 161mhz clock pdoi5- this symbol represents a transmission line of characteristic impedance z 0 = 50 ? . * required only if overhead circuit does not include internal input termination. 0.1 f 0.1 f 0.1 f 0.01 f 0.1 f +3.3v 0.1 f 0.1 f 100 ? * 100 ? * 100 ? * 100 ? * -3.3v limiting amp tia typic a l ope ra t ing circ uit 19-2624; rev 1; 5/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. part temp range pin-package max3953ugk 0 o c to +85 o c 68 qfn (10mm 10mm) pin configuration and functional diagram appear at end ofdata sheet. downloaded from: http:///
m ax 3 9 5 3 1 0 gbps 1 :1 6 de se ria lize r w it h cloc k re c ove ry 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage (v cc ) ............................................-0.5v to +5.0v input voltage levels (sdi+, sdi-) .................................(v cc - 1.0v) to (v cc + 0.5v) lvds output voltage levels (pdo[15..0], pclko+, pclko-) .........-0.5v to (v cc + 0.5v) voltage at lol , sync_err, rateset, clksel, refclk+, refclk-, refset, los_in, fil ............-0.5v to (v cc + 0.5v) continuous power dissipation (t a = 85c) 68-lead qfn (derate 30.3mw/c above +85c) ......... ...2.5w operating temperature range........................ ...... 0c to +85c storage temperature range .......................... ...-55c to +150c lead temperature (soldering, 10s) .................. ...............+300c processing temperature (die) ....................... ..................+400c dc electrical characteristics (v cc = +3.0v to +3.6v, t a = 0c to +85c. typical values are at +3.3v and t a = +25c, unless otherwise noted.) parameter symbol conditions min typ max units power supply supply current i cc 476 580 ma input specification (sdi+, sdi-) figure 1 differential input voltage v id ac-coupled or dc-coupled input 100 1200 mv p-p common-mode input range dc-coupled v cc - 0.3 v cc v input termination to v cc r in 40 50 60 ? reference clock input (refclk+, refclk-) (note 1) differential input voltage ac-coupled or dc-coupled input 300 1600 mv p-p lvpecl input high voltage v cc - 1.16 v cc - 0.88 v lvpecl input low voltage v cc - 1.81 v cc - 1.48 v lvpecl input bias voltage v cc - 1.3 v differential input impedance 2.6 k ? output specification (pdo[15..0] , pclko ) lvds output high voltage v oh 1.475 v lvds output low voltage v ol 0.925 v lvds differential output voltage ? v od ? 250 400 mv lvds change in magnitude of differential output for complementary states ?? v od ? 25 mv lvds offset output voltage v od 1.125 1.275 v lvds change in magnitude of output offset voltage for complementary states ?? v od ? 25 mv lvds differential output impedance 80 140 ? lvds output current short together or short to gnd 20 ma downloaded from: http:///
m ax 3 9 5 3 1 0 gbps 1 :1 6 de se ria lize r w it h cloc k re c ove ry _______________________________________________________________________________________ 3 ac electrical characteristics (v cc = +3.0v to +3.6v, t a = 0c to +85c. typical values are at +3.3v and t a = +25c, unless otherwise noted.) (note 2) dc electrical characteristics (continued) (v cc = +3.0v to +3.6v, t a = 0c to +85c. typical values are at +3.3v and t a = +25c, unless otherwise noted.) parameter symbol conditions min typ max units lvttl input and output (clksel, syn_err, rateset, los_in, lol , refset) lvttl input high voltage v ih 2v lvttl input low voltage v il 0.8 v lvttl input current -50 +6 a lvttl output high voltage v oh i oh = 20a 2.4 v cc v lvttl output low voltage v ol i ol = 1ma 0.4 v parameter symbol conditions min typ max units rateset = gnd 9.953 serial input data rate rateset = v cc 10.3125 gbps f = 400khz (notes 3, 4) 1.5 sinusoidal jitter tolerance f = 4mhz (note 3) 0.15 ui p-p tolerated consecutive identical digits bit-error ratio (ber) = 10 -12 2000 bits f < 10ghz, differential 10 f < 15ghz, differential 8 input return loss f < 15ghz, common mode 9 db frequency difference when pll indicates out of lock 1000 ppm frequency difference when pll indicates in lock 500 ppm lol assert time no transitions at input, figure 2 30 100 s pll acquisition time valid transitions at input, fig ure 2 100 s maximum pclko deviation from refclk 2500 ppm output clock to data delay t clk-q figure 3 -150 +150 ps output clock duty cycle 45 50 55 % note 1: reference clock duty cycle can range from 30% to 70 %. downloaded from: http:///
m ax 3 9 5 3 1 0 gbps 1 :1 6 de se ria lize r w it h cloc k re c ove ry 4 _______________________________________________________________________________________ note 2: guaranteed by design and characterization for t a = 0c to +85c. note 3: measured with 0.45ui p-p deterministic jitter and 0.15ui p-p random jitter, on top of the specified sinusoidal j itter in a 2 31 - 1 prbs pattern with a ber = 10 -12 . note 4: the jitter tolerance exceeds ieee 802.3ae specifica tions. the jitter tolerance outperforms the instrum ents measurement capability. ac electrical characteristics (v cc = +3.0v to +3.6v, t a = 0c to +85c. typical values are at +3.3v and t a = +25c, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units output clock and data rise/fall time t r , t f 20% to 80% 100 250 ps lvds differential skew t skew1 any differential pair 50 ps lvds channel-to-channel skew t skew2 pdo[15..0] 100 ps typic a l ope ra t ing cha ra c t e rist ic s (t a = +25c, unless otherwise noted.) recovered data and clock (0. 3gbps input) max3953 toc01 data 500ps/div clock supply current vs. tem perature max3953 toc02 temperature ( c) supply current (ma) 80 60 40 20 330 360 390 420 450 480 510 540 570 600 300 0 100 +3.6v +3.3v +3.0v max3953 toc03 input voltage (mv p-p ) bit-error ratio 20.5 20.0 19.5 19.0 18.5 10 -11 10 -10 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -12 18.0 21.0 bit-error ratio vs. input voltage max3953 toc04 frequency (khz) s 11 (db) 15,000 10,000 5000 -50 -40 -30 -20 -10 0 -60 0 20,000 differential s 11 vs. frequency jitter tolerance max3953 toc05 jitter frequency (khz) sinusoidal input jitter (ui p-p ) 100 1000 0.1 1 10 0.01 10 10,000 10gbps ethernet jitter tolerance measured with 0.45ui deterministic jitter and 0.15ui random jitter max3953 toc06 power-supply frequency (khz) jitter generation (ps rms ) 20,000 15,000 10,000 5000 1 2 3 4 5 6 0 0 25,000 jitter generation vs. power-supply frequency 100mv p-p sinusoid on v cc wideband jitter generation of pclko at 622mhz downloaded from: http:///
m ax 3 9 5 3 1 0 gbps 1 :1 6 de se ria lize r w it h cloc k re c ove ry _______________________________________________________________________________________ 5 pin de sc ript ion pin name function 1, 4, 5, 6, 14, 17, 18, 34, 35, 51, 52, 60, 68 gnd ground 2 refclk+ positive reference clock input, lvpecl. connect a b aud rate/64 or baud rate/16 reference clock. 3 refclk- negative reference clock input, lvpecl. connect a b aud rate/64 or baud rate/16 reference clock. 7 refset reference clock select input, ttl. when the referen ce clock is baud rate/64, set refset to gnd. when the reference clock is baud rate/16, set refse t to v cc . 8, 11, 12, 13, 15, 16, 27, 42, 59, 66 v cc +3.3v supply voltage 9 sdi+ positive serial data input, cml. 9.953gbps/10. 3125gbps serial data stream. 10 sdi- negative serial data input, cml. 9.953gbps/10 .3125gbps serial data stream. 19 los_in loss-of-signal input, ttl. the los_in is an external input. clock holdover is activated when los_in is ttl low. connect to v cc if los input is not available. see the acquisition controls section. 20 lol loss-of-lock indicator output, ttl. lol signals a ttl low when the vco frequency is more t han 1000ppm from the reference clock frequency. lol signals a ttl high when the vco frequency is within 500ppm of the reference clock frequency. see the acquisition controls section. 21 pclko+ positive parallel clock output, lvds 22 pclko- negative parallel clock output, lvds 23, 25, 28, 30, 32, 36, 38, 40, 43, 45, 47, 53, 55, 57, 61, 63 pdo15+ to pdo0+ positive parallel data outputs, lvds 24, 26, 29, 31, 33, 37, 39, 41, 44, 46, 48, 54, 56, 58, 62, 64 pdo15- to pdo0- negative parallel data outputs, lvds 49 sync_err synchronization error output, ttl. sync_err is inte nded to drive clksel for aquisition. see the acquisition controls section. 50 clksel output clock selector, ttl. clksel is the control i nput for aquisition. when clksel = gnd, pclko is derived from the input data. when clksel = v cc , pclko is derived from the reference clock. 65 rateset serial data rate select input, ttl. when the input serial data stream is 9.953gbps, set rateset to gnd. when the input serial data stream is 10.312gbp s, set rateset to v cc . 67 fil pll loop filter capacitor input. a capacitor betwee n this pin and v cc sets the loop to zero. a 0.047f capacitor is recommended. ep exposed pad ground. this must be soldered to the circuit board ground for proper thermal and electrical performance. see the layout considerations section. downloaded from: http:///
m ax 3 9 5 3 de t a ile d de sc ript ion the max3953 deserializer with clock recovery conver ts 9.953gbps/10.3125gbps serial data into 16-bit wide, 622mbps/644mbps parallel data. the device combines a fully integrated phase-locked loop (pll), ttl-compa tible status monitors, input amplifier, data retiming block, 16-bit demultiplexer, clock dividers, and lvds outp ut buffers. the pll consists of a phase/frequency dete c- tor (pfd), a loop filter, and voltage-controlled os cillator (vco). the pll recovers the serial clock from the i nput data stream and retimes the data. the demultiplexer generates a 16-bit-wide 622mbps/644mbps parallel data output. the max3953 is designed to deliver the best jitter performance by using differential signa l architecture and low-noise design techniques. i nput am plifie r the serial data input (sdi) amplifier accepts diffe rential input amplitudes from 100mv p-p to 1200mv p-p . pha se -fre que nc y de t e c t or the digital phase-frequency detector (pfd) aids fre quen- cy acquisition during startup conditions. depending on the polarity of the frequency input difference betw een refclk and the vco clock, the pfd drives the vco un til the frequency difference is reduced to zero. false locking is eliminated by this digital phase-frequency detec tor. the data phase detector is optimized to achieve 0.7 5ui high-frequency jitter tolerance. loop filt e r a nd v co the phase detector and frequency detector outputs a re summed into the loop filter. a 0.047f capacitor (c f ) is required to set the pll damping ratio. the loop fil ter output controls the on-chip vco. loss-of-loc k m onit or a loss-of-lock ( lol ) monitor is included in the max3953 frequency detector. a loss-of-lock condition is sig naled with a ttl low. when the pll is frequency locked, lol switches to ttl high in approximately 56s. lol signals a ttl low when the vco frequency is more than 1000ppm from the reference clock frequen- cy. lol signals a ttl high when the vco frequency is within 500ppm of the reference clock frequency. low -v olt a ge diffe re nt ia l signa l (lv ds) out put s the max3953 features lvds outputs for interfacing w ith high-speed circuitry. the lvds standard is based on the ieee 1596.3 lvds specification. this technology use s 500mv p-p to 800mv p-p differential low-voltage swings to achieve fast transition times, minimize power dissi pation, and improve noise immunity. applic a t ions i nform a t ion aquisit ion cont rols the max3953 has two phase-detector circuits, a bang - bang phase detector to lock the vco to the serial in put data (bb_pd), and a phase detector to lock the vco t o the reference clock (ref_pd). the pull-in range for the ref_pd is wide enough to accomodate the vco turn- ing range across the two valid data rates, while th e pull-in range for the bb_pd is narrow. the ref_pd is activated by clksel = high. the bb_pd is activated by clksel = low. for the max3953 cdr to lock to the serial input data, the frequency of the vco must be pulled within 500ppm of the input data rate by firs t lock- ing the vco to the reference clock (reclk) via the ref_pd. once the vco is within 500ppm, control can be transferred to the bb_pd. for normal operation, connect the sync_err output to the clksel input. this will force clksel high when the max3953 frequency detector indicates that the vco frequency is more than 500ppm from the refleck frequency. once the vco is pulled to within 500ppm of the refclk frequency, sync_err (and thus clksel) will go low and the max3953 will lock to the sdi data stream. if a loss-of-signal ( los ) input from the system is available to the max3953, a clock holdover operation can be i mple- mented by connecting the los output to the los_in input. this will force the pll to lock to refclk wh enever the incoming data is lost. this keeps the frequency of pclko from drifting during a loss-of-signal conditi on. if the los signal from the system is not available, or if the clock-holdover mode is not required, the los_in must be connected to v cc to disable the function. conse c ut ive i de nt ic a l digit s (ci ds) the max3953 has a low phase and frequency drift in the absence of data transitions. as a result, long runs of con- secutive zeros and ones can be tolerated while main tain- ing a ber of 1 ? 10 -12 . the cid tolerance is tested using a 2 13 - 1 pseudorandom bit stream (prbs), substituting a long run of zeros to simulate worst case. a cid tol erance of greater than 2,000 bits is typical. ex pose d-pa d pa c k a ge the exposed pad, 68-pin qfn incorporates features that provide a very low thermal-resistance path for heat removal from the ic. the pad is electrical ground o n the max3953 and should be soldered to the circuit board for proper thermal and electrical performance . see maxim application note hfan-08.1: thermal considerations of qfn and other exposed-paddle packages for further information. 1 0 gbps 1 :1 6 de se ria lize r w it h cloc k re c ove ry 6 _______________________________________________________________________________________ downloaded from: http:///
la yout t e c hnique s for best performance, use good high-frequency layou t techniques. filter voltage supplies, keep ground co n- nections short, and use multiple vias where possibl e. use controlled-impedance transmission lines to inte r- face with the max3953 high-speed inputs and outputs . power-supply decoupling should be placed as close t o the v cc as possible. to reduce feed-through, isolate input signals from output signals. m ax 3 9 5 3 1 0 gbps 1 :1 6 de se ria lize r w it h cloc k re c ove ry _______________________________________________________________________________________ 7 v cc - 0.3v v cc + 0.3v v cc - 0.6v v cc (b) ac-coupled cml input (a) dc-coupled cml input 600mv 600mv 50mv 50mv v cc - 0.3v v cc figure 1. input amplitude lol output lol assert time pll acquisition time input data 2 31 - 1 prbs 2 31 - 1 prbs figure 2. lol assert and acquisition time t clk-q t clk pclk+ pdo figure 3. timing parameters downloaded from: http:///
m ax 3 9 5 3 1 0 gbps 1 :1 6 de se ria lize r w it h cloc k re c ove ry 8 _______________________________________________________________________________________ div 16 d q 16-bit demultiplexer loop filter phase and frequency detector holdover state machine vco max3953 fil pecl cml lvds lvds lvds lvds ttl ttl ttl ttl ttl sync_err lol clksel pclko+ pclko- pdo15+ pdo15- pdo1+ pdo1- pdo0+ pdo0- refset refclk+ refclk- los_in sdi+ sdi- div n func t iona l dia gra m downloaded from: http:///
chip i nform a t ion transistor count: 11,612 process: sige bipolar m ax 3 9 5 3 1 0 gbps 1 :1 6 de se ria lize r w it h cloc k re c ove ry _______________________________________________________________________________________ 9 max3953 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 17 qfn* 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 34 33 * the exposed pad of the qfn package must be soldere d to ground for proper thermal and electrical operation. 38 39 40 41 42 43 44 45 46 47 35 36 37 48 49 50 51 58 59 60 61 62 54 55 56 57 63 top view 52 53 64 65 66 67 68 v cc lol fil v cc rateset pdo0- pdo0+ gnd pdo1- pdo1+ v cc pdo2- pdo2+ pdo3- pdo3+ pdo4- pdo4+ gnd los_in pclko- pclko+ pdo15- pdo15+ pdo14- pdo14+ pdo13+ v cc pdo12+ pdo13- pdo11+ pdo12- gnd pdo11- clksel sync_err pdo5- pdo5+ pdo6- pdo6+ pdo7- pdo8- pdo8+ pdo9- pdo9+ pdo10- pdo10+ pdo7+ v cc gnd sdi- v cc refset gnd gnd v cc v cc gnd v cc v cc sdi+ refclk- refclk+ gnd gnd gnd gnd gnd gnd pin configura t ion downloaded from: http:///
m ax 3 9 5 3 1 0 gbps 1 :1 6 de se ria lize r w it h cloc k re c ove ry maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________m a x im i nt e gra t e d produc t s, 1 2 0 sa n ga brie l drive , sunnyva le , ca 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0 ? 2004 maxim integrated products printed usa is a reg istered trademark of maxim integrated products. pa c k a ge i nform a t ion (the package drawing(s) in this data sheet may not reflect the most current specifications. for the la test package outline info rmation go to www.maxim-ic.com/packages .) downloaded from: http:///
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